PCB Design Interview Questions and Answers
by Bhavya Sri, on May 23, 2017 3:24:08 PM
Q1. Flow of Complete PCB design.
- Library creation
- Board outline and mechanicals
- Importing netlist
- Design Rule settings
- Component Placement
- Split plans
- Silkscreen and Assembly settings
- Gerber Settings
Q2. What are the inputs you need to design a PCB?
- We need schematic,bom and netlist(some pcb engineer generates netlist) from Hardware side and Board mechanicals from client i.e, board outline,mounting holes etc.
- and another important thing that we need is PCB stackup it is based on complexity of the board for example if we are using fpga first we should know number of signal layers need for fpga signal breakout.
Q3. How to create footprint?
Ans: Footprint flow:
- Padstack creation
- pin placement
- assembly outline
- silkscreen outline
- Place bound top (we can mention height of the here)
- dfa bound top
- no probe top
- silk and assembly reference designator
These are the basic things we need to create a footprint,follow IPC standards for proper guidelines.
Q4. Board mechanicals.
Ans: Draw board outline by considering client requirements,place mechanical hols and global fiducials.create route keepin and place keepin areas,
Questions that can be raised from this:
- size of the mechanical holes that you have used in your design and clearances that you have given to these.
- what are fiducials and use of these fiducials and types and differences between them.
- Fiducial placement and clearances.
- What are the clearances you have given from board outline to route and place keepin.
Q5. what are the errors you got while importing netlist?
- pcb footprint not found.
- pins mismatch between symbol and footprint etc.
Q6. How do you define design rules?
Ans: Design rules are nothing but creating tracewidth, spacing, vias limitations. Generally we get trace width and spacing details from stackup.
Q7. How do place components?
Ans: Place major components first i.e connectors, BGAs, mejor ICs then place other sections.
- How do you place connectors?
First check weather i.e right angle or it is right angle place at edge of the board and consider if there any recommendations from client.
Q8. How do you plan routing and what are the parameters you consider while routing?
Ans: Placement routing plays major roles in pcb design, quality of the board depends on placement and routing, good placement and routing can reduce your board fabrication cost also.
Place components by considering routing strategy and follow schematic flow once your placement is done do fanout for all the components, route high speed interfaces and complex areas first and maintain ground reference plane for all high speed signals and make sure that every trace has reference plane and try to reduce vias on signals vias can change trace characteristic impedance.
Which PCB/CAD tools does Freedom CAD use for layout?
Ans: Cadence Allegro: We have extensive experience with the Cadence Allegro tool suite; we currently support versions 15 and 16. We are proud to be one of a handful of Early Adopter Program Members with Cadence.
Q9. Mentor Graphics Expedition, Power PCB (PADS) and Board Station:
Ans: We currently support WG2004, EXP 2005.1, EXP 2005.3, EXP 2007 versions of Expedition, versions 2005sp1, 2005sp2 and 2009 of PADS and Board Station versions EN2002, EN2004, BSTN2005, BSTN2006, and BSXE2006. PADS 2007 is currently under evaluation for future support, please contact us for more information.
Valor Enterprise 3000: This is a cornerstone process tool for Freedom CAD to assure manufacturability and minimal delays in the fabrication process. We are a Valor Certified Design Partner.
Custom Programs: Over the past 10 years we have developed custom programs and scripts to gain efficiencies, improve quality and augment the current design tools.
Q10. How do you calculate the trace impedance of a PCB trace?
Ans: There are many methods. A formula method gives a quick result, though it is not highly accurate. A 2D Field solver gives more accurate result. The Trace impedance depends upon the width of the trace, separation from the ground / power plane, and the relative permittivity of the material.
Q11. What is the difference between a blind and buried via?
Ans: Blind vias are use to connect an inner layer to either the top or bottom layer. A buried via is used for connecting two inner layers. It does not go either to the top or the bottom layer. A regular via ( different from the blind and the buried via connects the top and the bottom layer and also passes through the inner layers.
Do not stop here. Go ahead and draw the diagram of the blind and the buried via.
Q12. What is the use of a decoupling capacitor?
Ans: A decoupling capacitor is used to smoothen the power supply noise. It should be placed as close to the ICs for which it is intended as possible.
Q13. What is DRC? What Kind of DRC errors you find in PCB Design?
Ans: DRC stands for Design Rule checking. A PCB should not have any electrical failure before we tape out for the manufacturing. Common DRC errors include, trace to pad violation, pad to pad violation, component keep out violation. Additionally a PCB Design may have high speed design rule related constraints. This may include, length matching constraints, differential signal length matching constraint.
Q14. What are the things you should do you ensure design for compliance for EMI?
Ans: We should use common mode chokes for all cables connectors. The common mode chokes should be placed as close to the connector as possible. The Power and ground planes should be as close to each other as possible. The High speed signal should refer to a ground or power plane and should not cross a split plane. Stitching capacitor should be used in case split plane is used.
Q15. A large thermal pad is divided into four sections? What is the use of it?
Ans: The open area between the 4 sections lead to escape of the gases during the reflow and soldering process. It leads to better manufacturability.
Q16. The width of a trace is increased ? Will its characteristic impedance increase of decrease ?
Ans: The Capacitance per unit length of the trace increases and therefore, the characteristic impedance of the trace decreases.
Q17. Robert, what are the most significant problems that you are seeing in PCB designs these days?
Ans: It's dependent on the design - whether it's high speed/low speed, high edge rate/lower edge rate, a simple PCB or large backplane design. However, some of the glaring problems are transmission line reflection due to the capacitive load; ground bounce; crosstalk between violent aggressors (like CMOS) and sensitive victims (like ECL/PECL and analog); bypassing and power delivery; common mode differential pair problems; and high speed clock loading.
Q18. How fast are the fastest boards you are seeing? How complex in terms of components and pins?
Ans: Several students in my classes are designing backplanes, servers and blades that have clock frequencies up to 11GHz. I consulted for a company that built a backplane with 65 BGAs having over 600 balls each, 34 layers and over 58K solder joints. The fastest digital board (not microwave) was an aerospace design running at 43 GHz. Regarding components, there is a BGA graphics processor with a clock speed of 5.6 GHz that has over 3400 balls. How would you like to reflow solder that one?
Q19. Day 1 of your seminar covers transmission lines. What are the most important points you'll be making?
Ans: The most significant thing would be defining the cutoff conditions to determine when a land trace acts like a transmission line versus a lumped circuit. This will determine to a large degree the termination scheme that will be used to minimize reflection. It is also important to define skin effect, dielectric loss and proximity effect. The interesting point about proximity effect is that if the spaces are just a fraction of the land width (like 5 to 1) this will create more signal loss than skin effect, dielectric and surface roughness combined.
Another subject is signal delay for microstrip and stripline. With microstrip, the delay is not the same for bare, solder mask covering and conformal covering (encapsulation over the solder mask). I'll also talk about providing the analysis for characteristic impedance and delay expressions for microstrips, buried microstrips, striplines and differentials.
Q20. What design techniques are needed to keep signal integrity under control?
Ans: Excellent communication between the EE design engineer, the PCB design engineer, the test engineer and manufacturing engineer is critical. Also, close coordination with the bareboard vendor and the EMS supplier is essential. The inputs from all of these will influence the best design techniques for achieving signal integrity. It is very important to conduct digital simulation (as with Cadence Allegro SI) and EMI/EMC simulation. The more up front the potential problem identification, the less debug time, the fewer problems during compliance testing, and the quicker the time to market.
Q21. What crosstalk problems are you seeing in high-speed designs (Day 2)?
Ans: High density board layout is very challenging. I have seen designs where 2s and 2s [2 mil-in wide land traces and spacing] are being used due to density/packaging restrictions. Interference between CMOS/TTL high edge rates and ECL/PECL is another problem. Yet another major concern is sensitive analog circuits in close proximity to the fast edge rate digital signals. This is where guard traces around the analog traces become effective.
Q22. How does crosstalk impact layer stacking?
Ans: To control crosstalk there has to be a distance between the aggressor and the victim versus the distance to the reference ground plane or power plane. Therefore, the tradeoff in many cases is how do I minimize my stackup layers (which is a cost consideration) versus controlling the crosstalk, and also the characteristic impedance, which is also a correlation between trace width and distance to the reference plane (or planes as in striplines).
As each new design is released there is typically a higher clock rate with higher edge rates, more signals per IC package, and a need for higher density that exacerbates crosstalk. In my estimation this will be one of the major challenges for the design community, as competition and cost considerations will highly influence the layer stacking.
Q23. What do designers need to do to ensure adequate power delivery within a specified power envelope (Day 3)?
Ans: In one word it's inductance. Designers need to identify how much inductance is inherent in the mounted capacitor loop and the ESL [equivalent series inductance] of the capacitor. The characteristics of the power and ground planes are also critical. Today cores are being produced with less than 1 mil-in of dielectric thickness. If these are used, they will enhance the power delivery, but at what cost?
Designers must know the bypassing capability of their output drivers. The only way to overcome SSO [simultaneous switching output] is at the die level. So designers need to provide the proper dq/dt at the needed IC pin at the right time.
Therefore, one must know the maximum level of power delivery noise allowed in the overall noise budget. With that knowledge the best strategy is to provide the correct IC die capacitance, inner plane capacitance, discrete capacitance and capacitor types (such as X2Y, Y cap, reverse electrode) to achieve this goal. Another factor, especially as frequency increases, is the anti/parallel resonance considerations that may require breaking up the capacitors into banks with different ESRs [equivalent series resistances] and different loop inductances.
Q24. What "best practices" do you advocate for differential signaling and clock distribution (Day 4)?
Ans: Probably the main concern is differential unbalance caused by the two lines not being the same electrical length. This causes common mode and is the main reason differentials can fail EMI radiation. Another consideration is to assign the more sensitive pairs as striplines. Avoid broadside layouts, that is, make them be edge to edge. Broadside layouts in many cases can render the design inoperable due to returning currents being contained on different ground planes, or possibly power planes, which can cause the receiver to see a totally different noise spectrum on its inputs.
Q25. When does EMI become a concern in PCB design, and what do designers need to know (Day 5)?
Ans: The two big concerns are radiated emissions and ESD [electro-static discharge]. All radiated emission formulas have both edge rate and frequency as two of the parameters. Therefore, many of the signal integrity rules also apply to EMI. The main cause of radiation from circuit boards is the size of the antenna loop -- that is, the pathway the current takes to the load and the direction/pathway that it takes to return to the VRM module. The more area this entails, the more radiation.
The designer must know the ESD pulse edge rate, which in turn will define the protection device (TVSS) or the filter. Another concern today is the ever increasing frequency, higher clock rates, and power dissipation in the design. Designs are becoming denser with more power dissipation. Due to the higher clock rates the apertures are decreasing in size to minimize harmonic radiation, meaning that the wavelengths are becoming shorter. However, with smaller apertures the design is much less efficient in allowing heat to escape the enclosure. This is one of the major concerns in EMI mechanical compatibility design.
Q26. What will each day of the seminar cover, and how will Cadence tools be demonstrated?
Ans: Each day at the conclusion of the training session, Cadence engineers will demonstrate examples of the lecture material. This will provide the student with real world examples of the methods used to design correctly. The following provides an itinerary of the courses.
TRANSMISSION LINES (Day 1): Fundamentals of transmission lines including stripline vs micro-strip. Cadence Demo: Pre- and post-route SI analysis using ideal and lossy transmission lines.
CROSSTALK (Day 2): Stack-up optimization and forward/reverse crosstalk. Cadence Demo: Pre- and post-route crosstalk analysis as well as crosstalk estimation.
POWER DELIVERY (Day 3): Proper use of decoupling capacitors and identifying power plane resonance. Cadence Demo: Allegro PCB Power Delivery Network (PDN) analysis
DIFFERENTIAL SIGNALING (Day 4): Loosely vs. tightly coupled differential pairs; clock distribution. Cadence Demo: Tandem and broad-side differential pair routing and analysis.
EMI/EMC (Day 5): Source, path, and receptor as well as how EMI/EMC tests are conducted. Cadence Demo: EM control rule checking and EMI net analysis.
Q27. What's your most important advice for clients working with high-speed digital boards?
Ans: One could write a book on this, but to briefly state the advice: know the rules of high speed design, work as a team in the prototype design, simulate the design, and work closely with the bare board vendor.