→ Lay a solid foundation for getting into detailed RTL learning exercises and related lab work.
→ Develop familiarity with the lab/project execution environment based on LINUX OS.
Overview of labs and projects that the students will conduct hands-on in the LINUX environment.
Overview of Verilog Primer Labs.
Main RTL quality considerations that a professional RTL designer must keep in mind while coding.
LAB1 : LINUX environment: Directory structure, basic commands, VI editor.
LAB1 : Quick-and-dirty compile and simulation of RTL using open-source Icarus Verilog and Gtkwave.
LAB1 : Compile RTL and bring-up simulations using ModelSim.
LAB2.1 : Example Code overview of File/IO/VCD example
Assignment: Execute LAB2.1